1. Field of the Invention
This invention relates generally to the structure and fabrication process of DMOS power devices. More particularly, this invention relates to a novel and improved DMOS device structure and fabrication process with double gate-oxide structure to reduce the gate/drain capacitance. The switching speed of the DMOS device is improved without degrading the breakdown voltage. Also, a low threshold voltage is maintained by controlling the ratio of layer thickness between the thick and thin gate oxide layers based on misalignment tolerance and body dopant profile.
2. Description of the Prior Art
The goal of increasing the switching speed by reducing the gate charges often causes other technical difficulties. Especially, when an oxide-terrace is used under the polysilicon gate for the purpose of reducing the gate/drain capacitance, degradation of the breakdown voltage is often induced. This is caused by the changes of the electrical field resulting from non-uniform insulation generated by placing a thick oxide layer underneath the polysilicon gates.
One specific example of such technical difficulties is disclosed in U.S. Pat. No. 5,273,922. It is entitled "High Speed Low Gate/Drain Capacitance DMOS Device", (issued on Dec. 28, 1993). As that shown in FIG. 3, Tsoi discloses a DMOS device with field oxide in the channel between adjacent transistors and an impurity implanted through the same opening in which the field oxide is formed. The gate is deposited over the field oxide and spaced from the supporting epitaxial layer by the field oxide to reduce the gate-to-drain capacitance. The implant impurity blow the field oxide reduces the on-resistance of the device. With these advantages intended by Tsoi's DMOS device, it is however limited by a difficulty that the breakdown voltage is degraded. Degradation of the breakdown voltage is illustrated in FIG. 2B. Actual breakdown voltage is measured for a DMOS power device provided with gate oxide layer with different thickness. The breakdown voltage BV is kept without significant change when the gate oxide layer is about one to four times the thickness of the normal gate oxide layer. The breakdown voltage starts to decrease rapidly when the gate oxide layer become greater than five times as that of the normal gate oxide layer.
In addition to the problem with breakdown voltage degradation, the DMOS device as disclosed by Tsoi has another technical difficulty. In forming the thick field oxide layer, a local oxidation process is employed. The oxidation of silicon proceeds slightly under the nitride. Due to the extremely thermal expansion-coeffident mismatch between the silicon nitride and the underlying silicon, damages are generated to the unoxidized silicon regions. In order to suppress this effect, a thin layer of silicon dioxide layer is grown prior to the placement of the silicon nitride mask This however aids to the penetration of the oxide under the nitride masked region and resulting in structures generally identified as "bird beaks" or "bird crests". (For more details of this phenomenon please refer to "VLSI Fabrication Principles" pp 576-581, by Ghandhi, published by Wiley-Interscience, New York). Additionally, during the growth of the field oxide, another phenomenon occurs that can cause defects later when the gate oxide is grown. Kooi et al. discovered that a thin layer of silicon nitride can form on the silicon surface, i.e., at the pad-oxide/silicon interface. This occurs due to the NH.sub.3 or some other NH compound or nitrogen is generated from the reaction between H.sub.2 O and the masking nitride during the field-oxide step. The NH.sub.3 then diffuses through the oxide and reacts with the silicon substrate to form silicon nitride spots or ribbon, often referred to as white ribbon. When the gate oxide is subsequently grown, the growth rate becomes impeded at the locations where such silicon nitride remains. The gate oxide layer is thinner at those locations than elsewhere. One way to overcome this problem is to either etch the pad oxide long enough to ensure that the ribbon is removed or to grow a wet sacrificial gate oxide. This sacrificial gate oxide is removed by wet etching before growing the final gate oxide layer. Sacrificial oxidation and post oxidation-etch is commonly employed prior to gate-oxidation as described above. However, for power MOSFET with large active area, these processing steps are very difficult to carry out to satisfy a low leakage current requirement. The chemical removal of the sacrificial oxide will again consume part of the field oxide and may cause structural defects between the interface between the thick field oxide and thin gate-oxide layer. Due to these structural defect at the interface between the thick and thin gate-oxide layers, a high gate-to-drain leakage current is induced.
Furthermore, Tsoi's device has another problem that the size of the transistors can not be further reduced to increase the cell density. The lateral dimension of a transistor cell is limited by a misalignment tolerance between the polysilicon gate and the field oxide. In order to avoid an increase in the device threshold voltage, the body regions must be kept at a certain distance away from the field oxide areas. However, since the body implant is not self-aligned to the field oxide, sufficient space has to be allowed to accommodate potential misalignment errors within the alignment tolerances. The lateral dimensions of the transistor are prevented from being further reduced due to this requirement.
Therefore, there is still a need in the art of power device fabrication, particularly for DMOS design and fabrication, to provide a structure and fabrication process that would resolve these difficulties.